Design for Testability (DFT), Boundary Scan, Built In Self Testing (BIST) Training 

Monday, April 19, 2010 – Wednesday, April 21, 2010

               ____________________________________________________

       The Test Connection, Inc. (TTCI)  

      11400 Cronridge Drive, Suite. H

      Owings Mills, Maryland 21117

What you will learn:

In this course learn all aspects of Design for Testability, from what it is, why it’s needed, why someone object to it, and what it can and cannot accomplish. Learn how today's technology has become elusive to certain failure modes and how important it is to expose them through testable designs. First, learn some simple techniques to enhance observability and controllability. Learn how to access hundreds of internal points with as few as four additional edge connector pins. Learn specific guidelines for both digital and analog circuit testability. Learn structured testability techniques, such as internal and boundary-scan. Come away with deep understanding of the IEEE 1149.1 (JTAG) standard's operation, use and even its limitations. Also learn some new techniques in testability, including IDDQ testing and I/O Mapping. Second, learn what built-in [self] test (BIST) is and how it can be specified. Learn structures such as linear feedback shift registers (LFSRs), signature analyzers, and pseudo-random signal generators. Use these building blocks to evaluate a number of BIST architectures. Learn BIT Software techniques and consider the effect false alarms have on BIT. Be able to specify BIT for your products and look at the possibilities of BIT taking over some of the ATE functions.

Abstract:

This is two courses combined into one. Part One, Design for Testability provides the guidelines necessary to improve circuit design from a test perspective. It includes simple and easy-to-implement ad-hoc testability guidelines. Then look at more sophisticated structured approaches to testability to place in ICs and boards. Special emphasis will be given to boundary-scan, the (JTAG) IEEE-1149.1. Analog circuit testability builds on the IEEE-1149.1, now the Mixed-Signal testability standard, designated as IEEE-1149.4. Examine this standard and the IEEE-1149.6 standard for AC Signal and transmission. Explore other related standards in development, such as the IEEE-1532, IJTAG and SJTAG. Part two, the course will cover Built-In Test. Starting with classification of Built-In Test approaches; the course introduces the building blocks of built-in self test (BIST) architectures. The course then examines some of these architectures, including Random Test Socket (RTS), the Built-In Logic Block Observer (BILBO), the Cyclic Analysis Testing Systems (CATS), the Built-In Test Exerciser and Sensor (BITES), and others. BIT software is also covered and a discussion on BIT false alarms is included. Finally, examine hierarchical approach to BIT, which offers a reduction if not elimination of ATE in both a manufacturing and maintenance environment.

Who should attend:

This is a design course, intended for designers and for those who motivate them for testability, such as test engineers. Managers concerned with testability issues will also find this course useful. Anyone interested in boundary-scan (JTAG/IEEE-1149.1) will agree with many of our graduates who called this the best course available on the subject. Since Built-In Test is becoming an issue of concern for top management as well as to marketing, this course - though a bit on the technical side - does examine applications for BIST in a product.

Detail:

DESIGN FOR TESTABILITY

Introduction to Design for Testability

What is Design for Testability?

Overview of Test Methodologies

• Flying Probe
• Boundary Scan
• Functional Test
• In-Circuit Test (ICT)

Quality As a Function of Yield and Test Coverage

Fault Models

Effect of Time-to-Market On Profits

Technical Goals of Testable Designs

Considerations for Testability

Approaches to Design for Testability

• Ad Hoc Design for Testability
• Structured Design for Testability
• Extended Design for Testability Or Built-In Self Test (BIST)

Design for Testability Attributes

• Controllability
• Observability
• Others

Basic Ad Hoc Design for Testability Rules

Controllability

• Controlling Buses
• Control of Large Fan-In
• Control Long Counters and Shift Registers

Observability

Testability Metrics

• SCOAP
• PCOLA/SOQ
• Sensitized Path Oriented Testability Scoring or  SPOTS (TM)

Design for Testability Techniques

Partitioning to Functionally Independent Sub-Systems

• Power Level Partitioning
• System Level Partitioning
• Mechanical Partitioning
• Partitioning Using Degating Circuits

Methods for Breaking Feedback Loops

Breaking Long Counters and Shift Registers

Methods for Breaking Free Running Clocks

Analog Testability

• Low Frequency (Under 50 kHz)
• High Frequency (50kHz - 100 MHz)
• RF

Testability for Memories

Design for Inspection (Inspectability)

Mechanical Design for Testability

Documentation for Testability

Other Testability Techniques

• Cross-Check
• I/O Mapping

I_DDQ Testing

• What is I_DDQ Testing?
• External Current Sensor
• Built-In Current Sensor
• Effectiveness of I_DDQ , Scan & Functional Tests

Evaluating Designs for Testability

• Dependency Models
• Testability Checklists
• Other Testability Analysis tools

Testability Standards and Guidelines

MIL-HDBK-2165

TMAG/Surface Mount Technology Association Testability Guidelines

IEEE-1149.x

Structured Design for Testability

Technical Goals of Testable Designs

General Structure of Scan

Scan Design Mode of Operation

• Level Sensitive Scan Design
• Scan/Set
• Random Access Scan
• Scan Features vs. Cost
• Full Scan vs. Partial Scan

Boundary Scan Structure

The Boundary Scan Cell and JTAG/IEEE-1149.1

Construction Of The Test Access Port (TAP)

• TAP Control Lines
• TAP Controller States
• Controller State Operation

Boundary-Scan Registers

Boundary-Scan Operational Modes

• Non-Invasive Operational Modes
• Pin Permission Operational Modes

Boundary-Scan Description Language (BSDL)

Boundary-Scan Tests

• Test Access Port (TAP) Integrity Test
• Wrong Component Test
• Boundary-Scan In-Circuit Test
• Virtual Interconnect Test
• Virtual Component or Cluster Test
• Boundary Functional Test

Mixed Signal  Boundary Scan Using the IEEE-1149.4

AC EXTEST Using the IEEE-1149.6

Other Testability Guidelines

• IEEE 1532
• IEEE P1687 (IJTAG)
• IEEE P1581
• IEEE 1500
• SJTAG

Evaluating Designs for Testability

Built-In Self Test

Technical Approach to BIST

Forms Of Built-In Self Test

• Continuous Monitoring (CM)
• Initiated Bit (I-BIT)
• Operational Readiness Test (ORT)

Elements of a BIST Architecture

Types of BIST

BIST Classification

BIST Using Error Detection Codes

Error-Correcting Codes

BIST Using Set/Scan Logic

• Signature Analyzer
• Pseudo-Random Signal Generator
• Linear Feedback Shift Register from Scan Cells
• Built-In Logic Block Observer (BILBO)

BIST Signal Generation tools

Test Generation Methods for BIST

BIST Response Collection tools

BIST Architectures

• Random Test Socket (RTS)
• Self-Testing Using MISR and Parallel SRSG (STUMPS)
• Centralized and Separate Board-Level BIST
• Built-In Evaluation & Self Test (BEST)
• Concurrent BIST Architecture
• Simultaneous Self Test (SST)
• Cyclic Analysis Testing Systems (CATS)
• Circular Self Test Path (CSTP)

BIST and BITE Architectures

• Redundancy BIT
• Wrap-around BIT
• Voltage Summing BIT
• Built-In Test Exerciser and Sensor (BITES)
• Exercisers and Sensors (EASs)

General Structure Of Non-Concurrent BIST

Built-in Test (BIT) Software

Why use BIT Software?

BIT Software Considerations

• Guidelines for Software BIT
• Selecting a Software Language
• Performance Monitoring Software

Failure Analysis Software

• Fault Filtering
• Heuristics in BIT

Evaluating BIT

Basic BIT and BITE Requirements

Self Checking BIT and BIST

BIT False Alarms

• Concerns of False Alarm
• BIT False Alarm Rate (BFAR)
• Causes of BIT False Alarms
• Overcoming False Alarms

BIT Specification

Manufacturing Test Strategies with Hierarchical BIT

Maintenance Test and Repair Strategies with Hierarchical BIT

What happens to ATE?

Instructors:

Bill Horner is introductory speaker.

Bill Horner is the President and C.E.O. of The Test Connection, Inc., leading application developer for ICT, Flying Probe, Boundary Scan and Functional Test. Bill has presented at the both Agilent Technologies, GenRad and Teradyne User's Groups. Mr. Horner is a member of the Loyola College's Center for Closely Held Firms and a member of the professional advisor committee for the Owings Campus of  ITT Technical Institute. Mr. Horner holds a B.S.E.E. and B.S. Applied Physics degree from the Loyola College and is a veteran of the U.S. Army. 

Louis Y. Ungar is the featured speaker

Louis Y. Ungar is president of A.T.E. Solutions, Inc., a leading independent test and testability consulting and educational firm. He has taught ATE and Testability courses at the University of California at Los Angeles (UCLA) and throughout industry. Mr. Ungar is a consultant to The American Society of Test Engineers, has served as Testability Chair for the Surface Mount Technology Association and has served on committees for various IEEE standards, including those of IEEE Std. 1149.x. Mr. Ungar holds a B.S.E.E. and Computer Science degree from the UCLA and has completed his course work towards a M.A. in Management.